The ID bit of the PSW is set to 0, the interrupt request is reset, and interrupt processing is enabled.
Possible causes are as follows:
- A mask is set for the interrupt (bit 6 of the interrupt control register is set).
- NMI processing is in progress (the NP bit of the PSW is set).
- Processing of a higher priority interrupt is in progress (check using the ISPR register).
- Consecutive instructions that do not acknowledge an interrupt exist.
Check the PSW, ISPR, and the interrupt control register.