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How to prevent FIFO when using E-DMAC?

Latest Updated:03/24/2009

Question:

When using DMAC (Direct Memory Access Controller) in burst mode, the transmit/receive FIFO error (Overflow or underflow) of E-DMAC (Ethernet Controller Direct Memory Access Controller) is sometimes generated. Please advise how to prevent this.

Answer:

Once DMAC acquires the bus right in burst mode, the bus right is not released until the transfer end conditions are satisfied.
Therefore, E-DMAC cannot acquire the bus right and the overflow or underflow error of transmit/receive FIFO may be generated.
Set DMAC to cycle-steal mode when using E-DMAC.
In cycle-steal mode, since the bus right is given to another bus master each time the DMAC transfer completes one transfer, it is passed from E-DMAC to DMAC to CPU to E-DMAC to… and the overflow and underflow of the transmit/receive FIFO can be prevented.
Suitable Products
SH-Ether
SH7618
SH7616
SH7615