Yes, it does. It must write arbitrary dummy data to the HVA0 register at the following points and the processor cannot access the HVA0 register at any other time.
1. When initializing the vector interrupt controller (VIC) after reset release (before the first interrupt occurs), one dummy write is required.
2. It is necessary to perform one dummy write just before completing each interrupt processing (ISR).
In the case of number 2, dummy writing to the HVA0 register must be finished before completion of interrupt processing (ISR) and will return to the original processing.
To complete the write process, it is recommended to use the DMB instruction just after a dummy write as following.
■Program description example (exact description depends on each compiler)
VIC.HVA0.LONG = 0x00000000;
For more details, refer to the HVA0 register page of the RZ/T1 Group User’s Manual: Hardware (R01UH0483) "12. Interrupt Controller (ICUA)".