In SPI boot mode, after returning from the reset state, boot processing starts by reading from the serial flash memory via the SPI multi-I/O bus controller (SPIBSC) with the settings shown below. Therefore, please change the settings for your product to meet the following conditions:
・ CPU clock (CPUCLK): 150 MHz
・ SPIBSC bit rate (SPBCLK): 18.75 MHz
・ Supported command: Read (03h)
・ Address output: 3 bytes
・ Dummy cycles: None
・ Data read width: 1 bit
・ SPI mode: CPOL = 0 (positive pulse)
CPHAR = 0 (data reception at odd edge)
CPHAT = 0 (data transmission at even edge)
Also, we recommend using a serial flash memory that has a dedicated reset pin, not multiplexed with any other function. If the reset pin is multiplexed with another pin function, make sure it is set to work as the reset function.
For more details, please refer to FAQ "Important Notes about SPI Boot Mode for RZ/T1".