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Why some devices write data before transmission and some can't?

Latest Updated:04/01/2006


Some devices can write the next data before transmission is completed while the others cannot write the next data until transmission is completed. Why?


This is because of the difference in configuration of the serial transmission block.
To execute serial communication, a parallel-to-serial conversion register is necessary because parallel data is written and output on a bit-by-bit basis.
If data is directly written to the conversion register and is converted into serial data, the structure is simple.

With this configuration, however, the conversion register is occupied while serial data is transmitted, which means that the next data cannot be written until all the bits have been transmitted.

To transmit multiple data, therefore, the following time is necessary.

Effective transfer time = Actual transfer time + Time from completion of transfer to preparation of next data

Even if the effective transfer rate is to be quickened, there is a restriction of the processing time of the CPU.
For improvement, some devices use a double buffer configuration that uses a register for writing, in addition to the conversion register.

With this configuration, the CPU writes data to the write register.
The data written to this register is transferred to the conversion register when the conversion register is empty.
The difference in timing between these two configurations is illustrated below.

If only the conversion register is used, the next data is written to the register when transmission has been completed.
In contrast, using the double buffer configuration can give the CPU sufficient processing time because the next data can be written even while the first data is transmitted.
Suitable Products
RL78 Family
78K Family