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How is the clock for the I2C port set within the SSP?

Latest Updated:10/04/2016

Question:

How is the clock for the I2C port set within the SSP?

Answer:

For the simple I2C driver, if you select the rate as Standard (100KHz) in the configuration, then the clock calculated by the low level function sci_siic_clock_settings() in synergy/ssp/src/driver/r_sci_i2c/r_sci_i2c.c gives N (p_brr) =36 and n (p_divisor) =0 (S7G2 with 120MHz PCLKA.

This ends up giving an actual clock setting of 101351.35 Hz. The clock setting that should be calculated is the one closest to the required clock, that is below the required clock rate, i.e. N (p_brr) =37 and n (p_divisor) =0, giving 98684.211 Hz. This error occurs due to rounding down by integer math that is used to calculate the clock rate:-

uint32_t temp_brr = SCI_SIIC_BRR_MIN;

and

temp_brr = clock_mhz / (p_baudinfo[i].div_coefficient * bitrate);