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When leaving unused pins open, how should the output latches be set?

Latest Updated:08/09/2007

Question:

(Pin, I/O Port)  When leaving unused pins open, how should the output latches be set? [2007/08/09]  

Answer:

D0-D3, P30, P31: Any value of output format and output latch is acceptable.
If a port input instruction (SZD, IAP0, IAP1, IAP2, IAP3) is executed while the output latch is 1, the supply voltage may be increased by the current flowing during the instruction execution cycle.

D4: Any value of output latch and N-channel open-drain output format is acceptable.
If a port input instruction (SZD, IAP0, IAP1, IAP2, IAP3) is executed while the output latch is 1, the supply voltage may be increased by the current flowing during the instruction execution cycle.
Do not select CNTR0 input as the timer 1 count source. (W11, W10 ≠ 0).

P00-P03, P10-P13: Disable key-on wakeup.
N-channel open-drain output instruction.
Any value of output latch is acceptable when the pull-up transistor is OFF.
If a port input instruction (SZD, IAP0, IAP1, IAP2, IAP3) is executed while the output latch is 1, the supply voltage may be increased by the current flowing during the instruction execution cycle.
Set the output latch to 1 when the pull-up transistor is ON.

P20, P21: Disable key-on wakeup.
N-channel open-drain output instruction.
Disable INT0 and INT1 pin input (I13 = 0, I23 = 0). Any value of output latch is acceptable when the pull-up transistor is OFF.
If a port input instruction (SZD, IAP0, IAP1, IAP2, IAP3) is executed while the output latch is 1, the supply voltage may be increased by the current flowing during the instruction execution cycle.
Set the output latch to 1 when the pull-up transistor is ON.

C: Any value of output latch and CMOS output format is acceptable. (#106683)

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