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What is the timing φ (internal clock) at clock frequency division bits?

Latest Updated:12/07/2004

Question:

(Clock)  What is the timing φ (internal clock) at the clock frequency division ratio selection bits (bits 7 and 6 in CPU mode register (003Bh))? [2004/12/07]

Answer:

Timing φ is as follows:
(b7,b6) = (0,0) : f(φ) = f(XIN) /2 (high-speed mode) : main clock (ceramic oscillation, RC oscillation)
frequency divided by 2
(0,1) : f(φ) = f(XIN) /8 (medium-speed mode) : main clock (ceramic oscillation, RC oscillation)
frequency divided by 8
(1,0) : supply from on-chip oscillator (on-chip oscillator mode) : on-chip oscillation frequency divided by 8
(1,1) : f(φ) = f(XIN) (double-speed mode) : undivided main clock (only in ceramic oscillation)

(#104931)

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