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What is the initial output level of the TxD pin?

Last Updated:12/26/2017

Question:

What is the initial level of the TxD pin when the serial I / O mode select bits (SMD 0 to SMD 2) of the UARTi transmit / receive mode register (UiMR) are set to each operation mode?

Answer:

Both initial levels of the TxD pin output "H" level from the time the clock synchronous serial I / O mode or UART mode is selected by the serial I / O mode select bits (SMD0 to SMD2) until transfer starts. However, when the NCH bit in the UiC0 register is 1 (N channel open drain output), the TxD pin goes into a high impedance state.
Suitable Products
R8C/18
R8C/19
R8C/1A
R8C/1B
R8C/20
R8C/21
R8C/22
R8C/23
R8C/24
R8C/25
R8C/26
R8C/27
R8C/28
R8C/29
R8C/2A
R8C/2B
R8C/2C
R8C/2D
R8C/2E
R8C/2F
R8C/2G
R8C/2H
R8C/2J
R8C/2K
R8C/2L
R8C/32C
R8C/33C
R8C/35C
R8C/36C
R8C/38C
R8C/3GC
R8C/3JC
R8C/32D
R8C/33D
R8C/35D
R8C/3GD
R8C/33T
R8C/38A
R8C/34E, R8C/34F, R8C/34G, R8C/34H
R8C/36E, R8C/36F, R8C/36G, R8C/36H
R8C/38E, R8C/38F, R8C/38G, R8C/38H