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How many times does DMA started signal till port data can be read?

Latest Updated:10/18/2004

Question:

I wish to know the minimum/maximum times from when DMA is started by an external signal (TIN edge input) till when port data is read in.

Answer:

The following shows a typical port data read timing in cases when DMA is started under the conditions listed below .

  • External bus and HOLD and LOCK instructions are unused
  • No access contention between DMA and SFR exists
[DMA settings]
  • External signal (TIN rising edge input) is selected for the cause of DMA start.,
  • Port data register is selected for the source address of transfer.
  • Internal RAM is selected for the destination address of transfer.

Fig 1. Reading timing of port data when DMA is started

In this case, the port input setup time is 100 ns at the minimum (same as the "Port input setup time"listed in the user's manual).

If access contention between DMA and SFR exists, DMA access may slow down from the above timing by 3 BCLK cycles at the most. For your reference, the following shows example timing in cases "(1) During normal access (access contention between DMA and SFR nonexistent)", "(2) When DMA and SFR contend for byte/half-word access", and "(3) When DMA and SFR contend for word access".

(1) During normal access (access contention between DMA and SFR nonexistent.

Fig 2. During normal access (access contention between DMA and SFR nonexistent)

(2) When DMA and SFR contend for byte/halfword access .

Fig 3. When DMA and SFR contend for byte/halfword access

(3) When DMA and SFR contend for word access.

Fig 4. When DMA and SFR contend for word access

Suitable Products
32170, 32174
32171
32172, 32173